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Altera_Forum
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18 years ago

modelsim 6.1g AE and port mapping

Hi everybody, machine_com : entity communication PORT MAP ( clk => sysclk, E_com(7 downto 0) => diag(7 downto 0), S_com(19 downto 9) => V_inter(19 downto 9) ); The port S_com i...
Altera_Forum's avatar
Altera_Forum
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18 years ago

The "entity" is the typo? This is weird. Perhaps you can try compile with -93 switch (e.g. vcom -93 ...)?