ModelSim -> Cannot open `include file

Thank you for your reply , fpgabuilder.

I have solved the path issue. Seems like there can't be any "space character" in the file data path.

I thought that I am compiling the file on the "C:/SDRAM_controller_ModelSim_test/" folder , but I compiled the wrong path "C:\Documents and Settings\Yuyex\Desktop\modelsim test1" :eek: (i compiled my backup files .. omG)

Here comes another issue from ddr_par.v which is still confusing me.

Error message :

1. (vlog-2155) global declarations are illegal in verilog 2001 syntax.

2. undefined variable: length_1.

3. 'length_1' already declared in this scope (work).

code (ddr_par.v):

// burst length

parameter length_1 = 3'b000;

parameter length_2 = 3'b001;

parameter length_4 = 3'b010;

parameter length_8 = 3'b011;

....

(so on)I cant use 'define since I still need some selection function on the parameter (at ddr_par.v), such as :

parameter num_clk_read = (mr_burst_length == length_1) ? 1 :

(mr_burst_length == length_2) ? 2 :

(mr_burst_length == length_4) ? 4 :

(mr_burst_length == length_8) ? 8 :

1; // default

From your last reply,

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a. How are you using the parameters? Are you using the parameters in the same module as you have the `include statement? Or are you using those parameters in blocks lower in the hierarchy?

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I am using ddr_par.v in all of the other .v files , that's why I have to use 'include in order to reduce the lines number.

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2.b. Also, something to look for is if you are using parameters as variables e.g. assign Length_1 = 3'd4;

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I'm using bit expression for this Length _1 since this bits will be sent to "SDRAM Load Mode Register" to initialize the characteristic of SDRAM itself.

Do you mean that it's better to use assign than parameter?

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2.c. Maybe your problem is not from the parameter declaration but the `define declaration after the code is successfully compiled. What if you enclose the argument to the defined term as (cs_clkcnt == NUM_CLK_tRP)

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This "global parameter" thing is the problem for now :((

Thank you in advance,

Yuyex:o