Forum Discussion
Altera_Forum
Honored Contributor
14 years agoTwo things may help further -
1. if you do not specify a path to the included file, then modelsim compiler assumes the file is located in the same folder from which you are running the compile. You can specify an include folder on the command line as - vlog module_to_be_compiled +incdir+C:/SDRAM_controller_ModelSim_test 2. Global declarations are illegal in Verilog 2001 syntax - I haven't seen this error myself, but I can think of a few pointers. Take it for what its worth. 2.a. How are you using hte parameters? Are you using the parameters in the same module as you have the `include statement? Or are you using those parameters in blocks lower in the hierarchy? 2.b. Also, something to look for is if you are using parameters as variables e.g. assign Length_1 = 3'd4; 2.c. Maybe your problem is not from the parameter declaration but the `define declaration after the code is successfully compiled. What if you enclose the argument to the defined term as (cs_clkcnt == NUM_CLK_tRP)