ModelSim -> Cannot open `include file

Thank you for your reply rbugalho,

At the beginning , I did what you said to me (ddr_par.v without module-endmodule), but i got error message : global declarations are illegal in verilog 2001 syntax.

From other forum , there's someone who said that most of verilog source code have module-endmodule. I know it but i don't think "this parameter file" needs it (am I wrong?) , but it is worthy to try, so I added module-endmodule into ddr_par.v .

And the idea of changing the directory of 'include is also comes from another forum too, but it didn't solve my problem.

Thank you in advance,

Yuyex:o