Modelsim –intel 10.5c reported a Fatal Error when I was simulating Intel FFT ip core

Hello,

Did you ever find a solution to this problem? I am running into the same error.

Here is a description of the problem:

1. The simulation runs initially but stops with a fatal error once the FFT begins sourcing samples
   
   # ** Fatal: (vsim-3421) Value -1 is out of range 0 to 4.
   # Time: 21980 ps Iteration: 1 Process: /ifft_tb/u0/auk_dspip_r22sdf_top_inst/r22sdf_core_inst/gen_natural_order_core/gen_stages(0)/r22_stage/gen_bfi/processing_bfi_cnt_p File: ./ifft_ip/simulation/submodules/mentor/auk_dspip_r22sdf_stage.vhd Line: 789
   # Fatal error in Process processing_bfi_cnt_p at ./ifft_ip/simulation/submodules/mentor/auk_dspip_r22sdf_stage.vhd line 789
   
   
2. From the beginning of the simulation, I get many warnings like this
   
   Warning: NUMERIC_STD."=": metavalue detected, returning FALSE
   # Time: 2500 ps Iteration: 1 Instance: /ifft_tb/u0/auk_dspip_r22sdf_top_inst/r22sdf_core_inst/gen_natural_order_core/gen_stages(0)/r22_stage/gen_bfii/bfii_inst/bf_control_inst
   
   I see in the waveform viewer that several signals in gen_natural_order_core/gen_stages(0)/r22_stage have undefined values: bfi_out_real, bfi_out_img, and twidaddr_s

So perhaps there's something wrong in generating the correct twiddle address? Or with generating the natural bit order?

I've generated theFFT IP core with the following parameters:

• Variable streaming
• Length = 128
• Natural Input Order
• Natural Output Order
• Direction = Bidirectional
• Fixed Point representation
• Data Input Width = 16 bits
• Twiddle Width = 32 bits
• Data Output Width = 16 bits

I am using:

• ModelSim Starter Edition 2020.1
• Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition

After generating the HDL, I created a TCL file "mentor.do" based on the template "msim_setup.tcl" (both attached).

I am running a simple testbench "ifft_tb.sv" (attached).

Thanks for any insight!

Thanks,

PBJ