Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Mixing Verilog and VHDL in Quartus II

I have a firmware project that was originally done in Verilog, and is still supported in that language. I am working on a variant, and would like to use some existing code that is in VHDL. Although ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

all you do is the same as in ISE - just write a component in the VHDL that maps to the verilog module and instantiate it. Quartus will work out the mapping fine.