Honored Contributor
Honored ContributorI'm in a hurry so..
- http://www.fpga4fun.com/crossclockdomain.html - I'm not sure what your question is... Constraning a clock eans you're telling TQ that that signal is a clock, with a 20 ns period (rising edge at 0 ns, falling edge at 10 ns by default). TQ will then use that information and it's knowledge of the internals of the FPGA to make sure your design meets the timing requirements (ie, does not violate setup or hold times). - input/output delay constrains are used to tell TQ what's going on outside the FPGA. set_input_delay -min 2 -clock clk [get_ports my_input] set_input_delay -max 3 -clock clk [get_ports my_input] ^^ This will tell TQ that the source of "my_input" will generate transitions on the rising edge of "clk" and the signal will be delayed 2..3 ns before reaching the FPGA's pin. set_output_delay -min 2 -clock clk [get_ports my_output] set_output_delay -max 3 -clock clk [get_ports my_output] ^^ This will tell TQ that "my_output" will be be delayed 2..3 ns after leaving the FPGA's pin and that the receiver will capture it on the rising edge of "clk". Note: You use "clk" in the I/O constraints not because your FPGA uses it, but because that's what your source/destination chip is using for those signals.
