missing .sdc file...

ok. i looked for the tutorial and found the Basic SDC Example

# Constrain clock port clk with a 10-ns requirement
create_clock -period 10 
# Automatically apply a generate clock on the output of phase-locked loops (PLLs)#  This command can be safely left in the SDC even if no PLLs exist in the design
derive_pll_clocks
# Constrain the input I/O path
set_input_delay -clock clk -max 3 
set_input_delay -clock clk -min 2 
# Constrain the output I/O path
set_output_delay -clock clk 2  2

question though, the 10ns period, what if i have, say, a 20Mhz clock, should the period be 50 ns.? what about the delay for the output, should i also put min and max value like in the input? i have an SPI-like clock for communication with a PIC microcontroller, do i have to use create_clock for that signal also? if use the SPI-like clock for inputs, should the delay in the input be based on that clock or the global clock?

thanks

BR

glenn