Minimum Pulse Width violation

Firstly, thank you for the prompt replies...

@Cris72: yes i want to be able to dynamically change the read-data latch clock. Upon power-up, a training algorithm is responsible for setting up the correct clock delay. I've set false paths between the core-clock and read-latch clock domains but the "minimum pulse width" violation is reported on the combinatorial and-or circuitry of the delay line.

@kaz: i understand that it is not good to mess with the clock, but the data-bus is 32-bit wide..

@Rysc: i guess you are referring to the dynamic delay chains of the device io-buffers. I am using a StratixII part that does not support this feature, thus i am using a proprietary programmable delay line.

Anyway it is not that a big deal, everything seems to be working OK.. thus i just have to ignore the timing-not-met warning.

Thank you again,

Kostas