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Altera_Forum
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15 years ago

Minimum Pulse Width violation

Hello, I have a design, where i am using a custom programmable delay line for shifting a clock. The delay line is implemented using and-or gates (as described in thread "Dynamic delay for LVDS ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

It looks like you are gating your clock. This is hard to survive in FPGA timing analysis. Minimum pulse width violation is distinct from tSU/tH violations and occurs at very high speeds or gated clocks. You better delay the data instead.