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annamalairaj's avatar
annamalairaj
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8 months ago

Minimum pulse width violation on EMIF-HPS

We are observing Minimum pulse width summary violation on three clocks in EMIF. Snapshots of Minimum pulse width violation on each of these clocks are attached.  Quartus version: 25.1.1  targeted F...
Timing
annamalairaj's avatar
annamalairaj
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2 months ago

Hi AdzimZM_Altera​ 

I have used Superior Performance with Maximum Placement Effort performance option and also tried the EMIF document optimize timing method by updating the Placement Effort Multiplier to 2 still same violation is observed.

I have also attached the HPS subsystem files. 

  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    Icon for Regular Contributor rankRegular Contributor
    1 month ago

    hi annamalairaj 

     

    I make hps_subsys as a top level, set the hps bridge as virtual pin and compile the design.

    I don't get the timing violation as you see.

    Can you try that from your end?