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annamalairaj's avatar
annamalairaj
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6 months ago

Minimum pulse width violation on EMIF-HPS

We are observing Minimum pulse width summary violation on three clocks in EMIF. Snapshots of Minimum pulse width violation on each of these clocks are attached.  Quartus version: 25.1.1  targeted F...
Timing
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
6 months ago

Hello annamalairaj,

 

Do you have any feedback in this thread?

 

Regards,

Adzim

annamalairaj's avatar
annamalairaj
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6 hours ago

Hi AdzimZM_Altera​ 

Sorry for the delayed response, and thanks for your patience. I wasn't able to follow up earlier. Regarding your questions:

  1. Can you share the connection of the EMIF HPS IP in Platform Designer?
    • Attached the image (emif_hps.png).
  2. What is the clock frequency you set in EMIF HPS IP?
    • 1200 MHz 
  3. Is there any SDC has been set to target this clock?
    • No.
  4. Is there any other IP than EMIF HPS IP in IO Bank 3C and 3D?
    • No, IO Bank 3C and 3D are dedicated only for EMIF HPS IP.
  5. Are you sharing the reference clock source for EMIF HPS IP?
    • No, we are not sharing this clock with any other blocks.