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Honored ContributorUpdate！hopefully get your help.
--- Quote Start --- Hi, all, During timing analisys I get unexpected minimum pulse width violation for clock signal with DQ_DQS2. I am using TimeQuest Timing Analyzer in Quartus II v14 and compile for Stratix V 5SGXEA7N2F45C2. Just minimum pulse width failed and others all passed. (setup,hold) Failing clock is a full rate core input clock for DQ_DQS IP module. 550MHz DDout DDRout( .reset_n_core_clock_in(Reset_N), .write_data_out(Dout), .output_strobe_out(K), .write_strobe_clock_in(clock_K_out), .output_strobe_n_out(K_n), .write_data_in(DQin), .write_oe_in(write_oe), .oct_ena_in(), .parallelterminationcontrol_in(parallelterminationcontrol_in), .seriesterminationcontrol_in(seriesterminationcontrol_in), .dll_delayctrl_in(dll_delayctrl), .fr_clock_in(clock_fr), // failling clock, from a PLL output .core_clock_in(), .hr_clock_in() ); Failed with two slow models:Slow 900mv 0C Model and Slow 900mv 85C Model but passed with two fast models:Fast900mv 0C Model and Fast 900mv 85C Model Failed type is Min-period and timing report as below, Clock cycle is 1.818ns, 550MHz, but required min-periond width is 2ns(500MHz) I checked device handbook and found min-period for should be less than 1ns(fmax > 1GHz) -0.182 1.818 2.000 Min Period clockout|pll550_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk Rise DDout:DDRout|DDout_0002:ddout_inst|altdq_dqs2_stratixv:altdq_dqs2_inst|output_path_gen[0].oe_reg -0.182 1.818 2.000 Min Period clockout|pll550_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk Rise DDout:DDRout|DDout_0002:ddout_inst|altdq_dqs2_stratixv:altdq_dqs2_inst|output_path_gen[10].oe_reg -0.182 1.818 2.000 Min Period clockout|pll550_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk Rise DDout:DDRout|DDout_0002:ddout_inst|altdq_dqs2_stratixv:altdq_dqs2_inst|output_path_gen[11].oe_reg -0.182 1.818 2.000 Min Period clockout|pll550_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk Rise DDout:DDRout|DDout_0002:ddout_inst|altdq_dqs2_stratixv:altdq_dqs2_inst|output_path_gen[12].oe_reg SDC file is as below , failling clock is clockout|pll550_inst|altera_pll_i|general[1].gpll~pll_output_counter|divclk set_time_format -unit ns -decimal_places 3 create_clock -name {clock_50} -period 20.000 -waveform { 0.000 10.000 } [get_ports {clock_50}] create_clock -name {CQ} -period 1.818 -waveform { 0.000 0.909 } [get_ports {CQ}] create_clock -name {CQ_n} -period 1.818 -waveform { 0.909 1.818 } [get_ports {CQ_n}] derive_pll_clocks create_generated_clock -name {create_generated_clock} -source [get_ports {CQ}] -duty_cycle 50.000 -multiply_by 1 -master_clock {CQ} [get_nets {clk_buf}] set_clock_latency -source 1.500 [get_clocks {clockout|pll550_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] # add latency to remove setup failure in timequest. minimum pulse width still failed even if remove this latency. derive_clock_uncertainty set_false_path -rise_from [get_clocks {clockout|pll550_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -to [get_clocks {clockout|pll550_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] set_false_path -fall_from [get_clocks {CQ}] -rise_to [get_clocks {create_generated_clock}] set_false_path -rise_from [get_clocks {CQ}] -rise_to [get_clocks {create_generated_clock}] attached qar project and qsf file. Could you help me about it? Any response will be appreciated. --- Quote End ---
