Minimum input frequency for Cyclone II PLLs

Question

I am going with a design propably coming with less than 10MHz oscillator frequency were some PLLs might be added in the future. I remember, that it has been said (somewhere in documentation) that there is a minimal input frequency required for the PLL to work properly.

What can be said about that?

altera_forum · Answer

When you use the PLL Megafunction wizard you are asked to enter the PLL input clock frequency. The wizard will automatically tell you if you are inside or outside the admitted range.

altera_forum · Answer

You can as well check the Cyclone II Handbook, Volume 1 Page 5-66  Lokla

altera_forum · Answer

Thanks, somehow I did not find that, however.

Forum Discussion

Minimum input frequency for Cyclone II PLLs

3 Replies

Recent Discussions

IOPLL related clock constraints

Failing IO buffer

Simulation using VWF

Minimum pulse width violation on EMIF-HPS

Licencing error for Questa - Altera FPGA Starter Edition 2025.2 (Quartus Prime Pro 25.1std)