Minimum II of 2 but HTML report has no further information

I could see double pumping not affecting load/store dependencies, but from an II perspective I think it should matter. Here's what I'm thinking, please let me know if you disagree: if I do two writes per loop at clock rate 'clk', and my memory is doublepumped such that it operates at 'clk2x' then on the first cycle of clk2x the first write will be performed, and on the second cycle of clk2x the second write will be performed. The writes will have been performed in order, and in 1 cycle of 'clk'.

Also, do you have any insight into why indirect address is bad in OpenCL? Is it just Altera preventing anyone from accidentally causing write collisions?

local float __attribute__((bankwidth(4),

numreadports(2),

numwriteports(2),

doublepump,

bank_bits(2,1,0))) mem[1024][4][2];

for (uint outer_outer = 0; outer_outer < 8; ++outer_outer)

{// some integer add,sub,and shifts that are used to help compute x_idx, y_idx later

float x_pipe[4];

float y_pipe[4];

uint x_idx_pipe[4];

uint y_idx_pipe[4];

for (uint outer = 0; outer < 8; ++outer)

{

uint x_idx, y_idx;

// compute x_idx, and y_idx using integer add, subs, and shifts

float x_fetched = mem[x_idx][0][0];

float y_fetched = mem[y_idx][0][0];

mem[x_idx_pipe[0]][0][1] = x_pipe[0];

mem[y_idx_pipe[0]][0][1] = y_pipe[0];

// manually coded shift register statements (i.e. no for loop) + computations on x and y

x_pipe[3] = x_fetched;

y_pipe[3] = y_fetched;

x_idx_pipe[3] = x_idx;

y_idx_pipe[3] = y_idx;

}

}