Migration from 10M08DCU324 to 10M16DCU324

I see that the question is the same for https://community.intel.com/t5/Intel-Quartus-Prime-Software/Migration-from-10M08DCU324-to-10M16DCU324/m-p/1683989#M86129.

I will let the https://community.intel.com/t5/Intel-Quartus-Prime-Software/Migration-from-10M08DCU324-to-10M16DCU324/m-p/1683989#M86129 taking care of the PLL related setting, while from Quartus tools perspective, do check the below:

Verify Quartus PLL Warning/Info Messages:

After compilation, carefully review the Quartus Messages window for:

PLL warnings

Compensation-related notices

Invalid frequency or out-of-range messages

If Quartus silently reconfigures an invalid setting, it’ll often warn about it.

onstrain the PLL Outputs

Add a clock constraint (create_clock) on c2 in the .sdc file:

create_clock -name c2_clk -period <period_in_ns> [get_ports c2_clk]

This makes sure Quartus respects timing paths using c2 and avoids removing or reconfiguring them unexpectedly.