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Altera_Forum
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11 years ago

Metastability test inside FPGA

Hi all! I'm working with DE-0 NANO and trying to create a simple design to show the importance of making timing constraints. I think it will be very representative if a part of design that do...
Altera_Forum's avatar
Altera_Forum
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11 years ago

kaz, thank you for your answer. As about timing in TimeQuest that is clear.

As I understand, your suggested scheme with two registers driven by one input should work like that: One register could go metastable and resolve '1' and second can resolve '0' and that is the error signal. Thank you!