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kaz, sorry, I have one more question. Is it true that, for example, to test input port of FPGA on metastability, I can use scheme (Figure 4. - Test Circuit Structure for Metastability Characterization)?
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No, that scheme is used to measure MTBF of fpga registers. It has its own two unrelated clock inputs. It is not about specific path measurement.
For a specific reg to reg path detection of metastability: first if your timing passes including correct io constraints then you can depend on tool's report and need not do any metastability detection.
If you are doing research then you can try a scheme based on xor say of two registers driven by one input (duplicates) and xor them to see if they sample differently. Just a thought!
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