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Altera_Forum
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11 years ago

Metastability test inside FPGA

Hi all! I'm working with DE-0 NANO and trying to create a simple design to show the importance of making timing constraints. I think it will be very representative if a part of design that do...
Altera_Forum's avatar
Altera_Forum
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11 years ago

kaz, sorry, I have one more question. Is it true that, for example, to test input port of FPGA on metastability, I can use scheme (Figure 4. - Test Circuit Structure for Metastability Characterization)?