Metastability test inside FPGA

Hi, kaz, thank you for your answer!

Did you mean Figure 4. - Test Circuit Structure for Metastability Characterization?

In that figure there are two destination registers, one rising_edge triggered and one falling edge triggered. And if the data after synchronizer is not the same on rising edge and the falling edge of the clkb, we will receive an error.

That can be, for example, if the synchronizer enters metastable state and resolves only after the falling edge of clkb, so then the next falling edge of a clkb occurs we will see an error.

But it is not representative as I think, it will be better if I can stop state machine or maybe reverse the counter. I mean, than some register enters metastable state, and we didn't isolate it from our code with a synhcronizer, we can make a code which will not work as we expect.

Our HDL code can only operate with '0' and '1', we can see that after metastable register resolves, our data can be not '0' but '1', or vice versa, and there will be a bug. That's will be a wrong detection. But I think (maybe I'm wrong), that there is a different type of bug generated by metastability. I mean, if our register that drives states of state machine, for example, receives a metastable value, it can direct us to the state, from which we cannot escape, for example. I mean what can happen, if our code makes a decision not after the metastable register resolves, but in time then it exactly outputs metastable value.