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Altera_Forum
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11 years ago

Metastability test inside FPGA

Hi all! I'm working with DE-0 NANO and trying to create a simple design to show the importance of making timing constraints. I think it will be very representative if a part of design that do...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

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Hi all!

I'm working with DE-0 NANO and trying to create a simple design to show the importance of making timing constraints.

I think it will be very representative if a part of design that doesn't meet timing, falls into a metastable state and after that a problem will be fixed adding constraints.

Can someone help me with any ideas, how to create a code which will mostly representative crashes if a metastable situation occurs (internal counter stops, dead state enters, etc)?

And how to visualize it better (signal tap, signal probe, iLEDs maybe).

Thanks in advance.

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There is one here:

http://www.google.co.uk/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&ved=0ccqqfjaa&url=http%3a%2f%2fwww.altera.co.uk%2fliterature%2fwp%2fwp-01082-quartus-ii-metastability.pdf&ei=yvi0vie9d_om7abliyg4bw&usg=afqjcng_grhb27s1lwq24tre8frbxhbila&sig2=gzpxe4z9iaqyeud6gle80q