Forum Discussion
DmitryKo
New Contributor
2 years agoMessage Waiting for clock in Signal tap for input external clock
Hi, all I am using Quartus Prime Standard Edition version 16.1.2 Build 203 Device Cyclone V 5CEBA8F23C8 Approximately in more than 50 % of compilations of my project I got message Waiting for cl...
sstrell
Super Contributor
2 years agoWhy don't you use an output clock of the PLL for your capture clock instead of the input reference clock? The output clock is what is used to clock your logic anyway (I presume) so that should be the clock you use for Signal Tap.