Memory Mapped Master interface in Qsys lacks associated reset

I meet some problem when i using the qsys to complete a simple design.My design includes 3 component.The first one is custom_masters_hw.tcl downloaded from the website.The second one is generated by the pwm.v which matchs avalon-mm slave port.The third one is generated by the userlogic.v .When I click Generate button in the qsys, I get an error message stating that the " Interfaces sim_inst_master_template_0_user_bfm.conduit and sim_inst.master_template_0_user must have matching associated resets, but sim_inst_master_template_0_user_bfm.conduit has no associated reset."I want all of the simulation model,testbench,synthesize and bfm model.

The pwm.v and userlogic.v are in the source folder.All the other source are in the folder.Please help me.