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Honored ContributorMemory initialization file
Dear my best friends
My project use Cyclone II family (EP2C70F896C6 board) The memory initialization file have 16bit (width) This is my code for reading memory file:LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
LIBRARY lpm;
USE lpm.LPM_COMPONENTS.ALL;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_signed.all;
ENTITY sin_cos625 IS
PORT (
CLK : IN STD_LOGIC:='0';
CMD_ID,CMD_IQ, ADDRESS : IN STD_LOGIC_VECTOR(15 downto 0):=(others =>'0');
Vref1,Vref2,Vref3 : OUT STD_LOGIC_VECTOR(15 downto 0):=(others =>'0')
);
END sin_cos625;
ARCHITECTURE sin_cos625_arch OF sin_cos625 IS
signal sin_addr, cos_addr : STD_LOGIC_vector(15 downto 0):=(others =>'0');
signal sin_teta, cos_teta : STD_LOGIC_VECTOR (15 downto 0):=(others =>'0');
signal PO_SIN,PO_COS,NT_SIN: STD_LOGIC_VECTOR (15 downto 0):=(others =>'0');
signal CNT : STD_LOGIC_VECTOR (7 DOWNTO 0):=(others =>'0');
signal Adda, Addb, Addr, Mula, Mulb: STD_LOGIC_VECTOR (15 downto 0):=(others =>'0');
signal Mulr : STD_LOGIC_vector(31 downto 0):=(others =>'0');
signal CMD_Vbeta, CMD_Vbetaa, CMD_Valpha: STD_LOGIC_vector(15 downto 0):=(others =>'0');
signal Vrefx, Vrefy, Vrefz : STD_LOGIC_vector(15 downto 0):=(others =>'0');
BEGIN
u1 : lpm_rom
GENERIC MAP(lpm_width => 16, lpm_widthad => 16, lpm_file => "Sin.mif",
lpm_address_control => "REGISTERED", lpm_outdata => "UNREGISTERED")
PORT MAP(ADDRESS => sin_addr, inclock => clk, q => sin_teta);
u2 : lpm_rom
GENERIC MAP(lpm_width => 16, lpm_widthad => 16, lpm_file => "Cos.mif",
lpm_address_control => "REGISTERED", lpm_outdata => "UNREGISTERED")
PORT MAP(ADDRESS => cos_addr, inclock => clk, q => cos_teta);
mull: lpm_mult
generic map(LPM_WIDTHA=>16,LPM_WIDTHB=>16,LPM_WIDTHS=>16,LPM_WIDTHP=>32,LPM_REPRESENTATION=>"SIGNED",LPM_PIPELINE=>1)
port map(dataa=> mula,datab=> mulb,clock=> clk,result=> mulr);
adder1: lpm_add_sub
generic map(lpm_width=>16,LPM_REPRESENTATION=>"SIGNED",lpm_pipeline=>1)
port map(dataa=>adda,datab=>addb,clock=> clk,result=>addr);
-- Enter sin_addr and cos_addr and lpm will give the value at sin_teta and cos_teta
GEN : block
begin
process (CLK)
begin
if CLK'event and CLK='1' then
CNT<=cnt+1;
IF CNT = x"00" then
sin_addr <= ADDRESS;
cos_addr <= ADDRESS;
ELSIF CNT=x"02" THEN
IF sin_teta = x"000" THEN
NT_SIN <= x"FFF";
PO_SIN <= x"000";
ELSE
NT_SIN <= -sin_teta;
PO_SIN <= sin_teta;
END IF;
PO_COS <= cos_teta;
ELSIF CNT=x"04" THEN
MULA <= CMD_ID;
MULB <= PO_SIN;
ELSIF CNT=x"06" THEN
ADDA <= MULR(15 DOWNTO 0);
MULA <= CMD_IQ;
MULB <= PO_COS;
ELSIF CNT=x"08" THEN
ADDB <= MULR(15 DOWNTO 0);
MULA <= CMD_ID;
MULB <= PO_COS;
ELSIF CNT=x"0A" THEN
MULA <= CMD_IQ;
MULB <= NT_SIN;
CMD_Vbeta <= ADDR;
Vrefx <= ADDR;
ADDA <= MULR(15 DOWNTO 0);
ELSIF CNT=x"0C" THEN
ADDB <= MULR(15 DOWNTO 0);
CMD_Vbetaa <= CMD_Vbeta(15) &'0'& CMD_Vbeta(13 downto 0);
ELSIF CNT=x"0E" THEN
CMD_Valpha <= ADDR;
MULA <= ADDR;
MULB <= x"06EE";
ELSIF CNT=x"10" THEN
ADDA <= -CMD_Vbetaa;
ADDB <= MULR(15 DOWNTO 0);
ELSIF CNT=x"12" THEN
Vrefy <= ADDR;
ADDA <= -CMD_Vbetaa;
ADDB <= -MULR(15 DOWNTO 0);
ELSIF CNT=x"14" THEN
Vrefz <= ADDR;
ELSIF CNT = x"16" THEN
Vref1 <= Vrefx;
Vref2 <= Vrefy;
Vref3 <= Vrefz;
CNT <= x"00";
END IF;
END IF;
end process;
end block GEN;
END sin_cos625_arch;
