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have run into an issue where one of the megafunction-generated VHDL files seems to have an error in it, and I was wondering if anyone on here could help figure out what is causing it. I dont really know much VHDL, so I was wondering if someone could explain to me why this isnt working. Also, I have not edited the VHDL file at all. Any help would be great!
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That is not VHDL. I suspect its probably AHDL (Altera's language).
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Error: Text Design File syntax error: Text Design File contains MEMORY where a symbolic name or a number was expected
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Perhaps MEMORY is a reserved keyword, and the syntax checker is not smart enough to tell you that. Try changing the name to RAM0.tdf and see what happens.
Cheers,
Dave
Honored Contributor
