MAX10 UFM timing

I inverted it. It should be that if waitrequest is high, data transfer is delayed. The command (address and read or write control signal) must be held until waitrequest goes low. One cycle after that, the data transfer occurs.

See the Avalon spec: https://www.intel.com/content/www/us/en/docs/programmable/683091/22-3/introduction-to-the-interface-specifications.html

As for your simulation there, perhaps it's a burst transfer? It's not clear without knowing all the signals involved.