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Michael_Ford
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2 years ago

MAX10 UFM timing

I am simulating an interface with Max10 UFM and having readdata output delayed by one clock cycle more than what is shown in Intel MAX 10 UFM Implementation Guides. Is the timing provided incorrect? ...
Simulation
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Michael_Ford
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1 year ago

Another odd behavior. After an erase operation completes I see the status data change without even doing a read.

Thought maybe I could keep avmm_csr_read high to continuously monitor status for 01=BUSY_ERASE to clear but why does it change when read is low?