Forum Discussion
Michael_Ford
New Contributor
2 years agoMAX10 UFM timing
I am simulating an interface with Max10 UFM and having readdata output delayed by one clock cycle more than what is shown in Intel MAX 10 UFM Implementation Guides. Is the timing provided incorrect? ...
Michael_Ford
New Contributor
1 year agoI had thought the avmm_data_waitrequest was only applicable to the data register not the control register. Waitrequest is not shown in timing diagrams for reading of control register in the UFM User Guide. Diagram shows output on next clock after avmm_csr_read goes high. However I do see waitrequest get asserted in the simulation when the control register data becomes valid so maybe that is the issue. In which case the documentation seems misleading. Thanks.