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Michael_Ford's avatar
Michael_Ford
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2 years ago

MAX10 UFM timing

I am simulating an interface with Max10 UFM and having readdata output delayed by one clock cycle more than what is shown in Intel MAX 10 UFM Implementation Guides. Is the timing provided incorrect? ...
Simulation
sstrell's avatar
sstrell
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2 years ago

It's an Avalon interface. You should be monitoring the waitrequest signal as well. If waitrequest is low, data transfer is delayed.