New ContributorHi,
AN745 in "Table 1. I/O Standards for MIPI D-PHY Implementation" requires "Differential HSTL-1.8" for high speed pins. However Quartus compilation fails...
According to the MAX10 device handbook, the chip supports "Differential HSTL-1.8".
Is this feature available for all high speed pins?
Thank you
Regular ContributorHello,
Yes you can refer to page 22 from this document: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/m10_datasheet.pdf
Thanks.
New ContributorHi AminT
thank you for your reply.
Indeed the document specify the VOL/VIH ranges, but it seems not referring to which set of IOs support Differential HSTL.
Is there any clarification on that?
Would all the pin marked as DIFFIO / DIFFIO_TX / DIFFIO_TX_RX support Differential HSTL?
Thank you
Regular ContributorHello,
It depends. You may refer to pin-out files from this link of your device: https://www.intel.com/content/www/us/en/programmable/support/literature/lit-dp.html
Thank you.
