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luca5's avatar
luca5
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5 years ago

MAX10 Differential HSTL-1.8 for MIPI CSI2 TX

Hi, AN745 in "Table 1. I/O Standards for MIPI D-PHY Implementation" requires "Differential HSTL-1.8" for high speed pins. However Quartus compilation fails... https://www.intel.com/content/www/us...
luca5's avatar
luca5
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5 years ago

Hi AminT

thank you for your reply.

Indeed the document specify the VOL/VIH ranges, but it seems not referring to which set of IOs support Differential HSTL.

Is there any clarification on that?

Would all the pin marked as DIFFIO / DIFFIO_TX / DIFFIO_TX_RX support Differential HSTL?

Thank you

  • luca5's avatar
    luca5
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    5 years ago

    Hi Amin,

    thank you for the hint. For instance, that means pins marked

    DIFFIO_RX_L5n
    DIFFIO_RX_L6n

    are not differential TX/RX but just differential RX capable pins, correct?

    Thank you

    • AminT_Intel's avatar
      AminT_Intel
      Icon for Regular Contributor rankRegular Contributor
      5 years ago

      Hello,

      Yes you are right!

      Thanks

      • AminT_Intel's avatar
        AminT_Intel
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        5 years ago

        I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.