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MAYLIS's avatar
MAYLIS
Icon for New Contributor rankNew Contributor
5 years ago

MAX10 ADC (Quartus)

Hi, I configured the ADC of the MAX10 on Quartus, I powered it but I am stuck in the initialization of this last one, I wrote a code to initialize it but I still cannot have the data. It's in sample_store_csr_readdata where there are the samples, I put the address to 0x0000000 and the read to 1 and to initialize the ADC I put the address to 0x0, write to 1 and writedata to 1 because bit 0 corresponds to the initialization of the ADC.

Thanks

5 Replies

  • Ash_R_Intel's avatar
    Ash_R_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi,

    Thanks for sharing the code.

    The problem is that there is no handshake mechanism between data_initialisation entity and the ADC IP.

    Once you give a Run command, you need to wait for the sample_store_irq_irq signal from the IP to indicate that the digital data is ready to be read.

    Then you should initiate a read command to the sample store csr interface to get that digital data.

    After initiating the read expect the data at the next clock edge from when the csr interface gets the read command. This is due to Avalon-MM interface latency.


    Regards.


    • MAYLIS's avatar
      MAYLIS
      Icon for New Contributor rankNew Contributor
      5 years ago

      Thanks a lot, I'll try it.

      Regards

    • MAYLIS's avatar
      MAYLIS
      Icon for New Contributor rankNew Contributor
      5 years ago

      Hello !!

      Thanks for your reply. Exactly, to run it, I have to set bit 0 to 1, I am attaching a screenshot of the datasheet.

       

      Here is my code for the initialization, I put also the sample_read to 1 so that I can activate data reading that I will recover them then with a PIO, but I still don't succeed I don't know the error it comes from where :

      library IEEE;
      use IEEE.std_logic_1164.all;
      use IEEE.numeric_std.all;
      --------------------------------------------------------------------------------------------------------------
      entity data_initialisation is
      port(
      clk : in std_logic;
      sequencer_address : out std_logic := 'X'; -- address
      sequencer_read : out std_logic := 'X'; -- read
      sequencer_write : out std_logic := 'X'; -- write
      sequencer_writedata : out std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
      -- sequencer_readdata : in std_logic_vector(31 downto 0) ; -- readdata
      sample_store_address : out std_logic_vector(6 downto 0) := (others => 'X'); -- address
      sample_store_read : out std_logic := 'X'; -- read
      sample_store_write : out std_logic := 'X'; -- write
      --sample_store_writedata : out std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
      sample_store_readdata : in std_logic_vector(31 downto 0) -- readdata
      );
      end entity data_initialisation;
      --------------------------------------------------------------------------------------------------------------
      architecture behavioral of data_initialisation is
      signal register_samples : std_logic_vector(31 downto 0);
      signal sequencer_readdata : std_logic_vector(31 downto 0) ; -- readdata
      signal sample_store_writedata : std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
      type seq_FSM_state_machine is (idle, write_CSR_sequencer, read_samples);
      signal seq_FSM : seq_FSM_state_machine := idle;
      begin
      seq : process ( clk)
      begin
      if clk'event and clk = '1' then
      case seq_FSM is
      when idle =>
      seq_FSM <= write_CSR_sequencer;
      when write_CSR_sequencer =>
      seq_FSM <= read_samples;
      when read_samples =>
      seq_FSM <= read_samples;
      end case;
      end if;
      end process;
      process ( seq_FSM)
      begin
      case seq_FSM is
      when idle =>
      sequencer_address <= '0';
      sequencer_read <= '0';
      sequencer_write <= '0';
      sequencer_writedata <= (others => '0');
      sample_store_address <= std_logic_vector(to_unsigned (16#0000#, sample_store_address'length));
      sample_store_read <= '0';
      sample_store_write <= '0';
      when write_CSR_sequencer =>
      sequencer_address <= '0';
      sequencer_read <= '0';
      sequencer_write <= '1';
      sequencer_writedata <= x"00000001";
      when read_samples =>
      sample_store_address <= std_logic_vector(to_unsigned (16#0000#, sample_store_address'length));
      sample_store_read <= '1';
      register_samples <= sample_store_readdata ;
      sample_store_write <= '0';
      when others =>
      sequencer_address <= '0';
      sequencer_read <= '0';
      sequencer_write <= '0';
      sequencer_writedata <= (others => '0');
      sample_store_address <= std_logic_vector(to_unsigned (16#0000#, sample_store_address'length));
      sample_store_read <= '0';
      sample_store_write <= '0';
      end case;
      end process;
      end architecture behavioral;
      To read data with the PIO, I just put an IORD of the PIO on eclipse, I don't know if this is what I should do or it is necessary to write a function to increase the addresses by 4 and after reading the value.
      Thanks in advance.
      Regards,