MAX10 ADC (Quartus)

Hi,

Thanks for sharing the code.

The problem is that there is no handshake mechanism between data_initialisation entity and the ADC IP.

Once you give a Run command, you need to wait for the sample_store_irq_irq signal from the IP to indicate that the digital data is ready to be read.

Then you should initiate a read command to the sample store csr interface to get that digital data.

After initiating the read expect the data at the next clock edge from when the csr interface gets the read command. This is due to Avalon-MM interface latency.

Regards.