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RobGS's avatar
RobGS
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5 days ago

MAX10 ADC - getting it to simulate in Modelsim

Hi,

I'm setting up a new project - actually a rework of a 7 year old project were we had massive tools problems with the ADC, some of which I think were specific to Quartus 17.

I have regenerated the ADC IP in Quartus 18.1.
I have manually created the simulation in Modelsim 10.5b.

I have added all the ADC files I can find to the Modelsim project, as shown in the attached screenshot.
When I run the simulation, all the ADC outputs are floating.

Any clues as to what I am going wrong, please?

I tried running the msim_setup.tcl from the Modelsim command line, but this made no difference.

Searching this forum, I wonder if it has something to do with fiftyfivenm_adcblock_primitive_wrapper.v, but the solution eludes me, since I have compiled this.

Attached:
screenshot of my modelsim project, the generated IP code, and my vhdl which instantiates the ADC.

Thanks,

Rob

Simulation

1 Reply

  • ZiYingE_Altera's avatar
    ZiYingE_Altera
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    1 hour ago

    Hi Rob, 
     

    May I confirm whether you are currently using Quartus Prime Lite Edition 18.1?

     

    Could you also confirm the ModelSim version and edition being used? From your previous information, it appears to be ModelSim Intel FPGA Starter Edition 10.5b? 
     

    To better understand the ADC issue, could you please provide the following details?

    • Are there any error or warning messages during simulation?
    • Could you share a screenshot of the simulation waveform?
    • Is this issue only observed in Quartus Prime Lite 18.1, or does it also occur in Quartus 17.1?

    From the screenshot attached, all of the ADC was added directly into your ModelSim project, which means they will be compiled into the default work library. The MAX 10 ADC IP requires files to be compiled into separate libraries for the cross-language (VHDL→Verilog) binding to work. 

    According to the generated msim_setup.tcl script, the required simulation libraries and compilation order have already been defined for the design.

     

    Here are a few suggestions that may help further troubleshoot the issue:
    1. You mentioned that running msim_setup.tcl previously made no difference. Could you please try the following steps again from the simulation/mentor/ directory again?
    set QUARTUS_INSTALL_DIR "/path/to/your/quartus/18.1/quartus" 
    source msim_setup.tcl 
    ld_debug

    2.  Could you also please check QUARTUS_INSTALL_DIR is pointing to the correct Quartus installation path before sourcing the script? The generated script appears to reference:

    C:/apps/intelfpga_lite/18.1/quartus/

    3. If the ADC outputs are still floating after the above steps, could you try regenerating the ADC IP with Verilog selected as the simulation language?

    According to the MAX 10 Analog-to-Digital Converter User Guide, the Modular ADC core supports generation of Verilog simulation scripts only:

    https://docs.altera.com/r/docs/683596/24.1/max-10-analog-to-digital-converter-user-guide/fixed-adc-logic-simulation-output 

    Feel free to share the results when you have them, and I'll be happy to help with the next steps. Thank you! 

    Regards, 
    ZiYingE_Altera