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Altera_Forum
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11 years ago

MAX V - Reliability in design issues

Hello, I am having trouble to develop a consistent/reliable program on a CPLD MAXV reference 5M2210ZF256C5. I am using the free version of Quartus v13.1.3 64Bits. The input clock of the...
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Altera_Forum
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11 years ago

Generate an 'enable' signal that is active every 8th clock and use it to qualify all the logic that needs to run at 12.5MHz