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Altera_Forum
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11 years ago

MAX V - Reliability in design issues

Hello, I am having trouble to develop a consistent/reliable program on a CPLD MAXV reference 5M2210ZF256C5. I am using the free version of Quartus v13.1.3 64Bits. The input clock of the...
Altera_Forum's avatar
Altera_Forum
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11 years ago

You have an combinationally generated clock, which is likely to fail due to glitches even if there are no domain crossing signals between i_clock and SAWTOOTH_CLOCK domain. 

SAWTOOTH_CLOCK <= '1' when ( cont_reg < 3 ) else '0';

At this point I stopped checking for possible additional design issues. I guess, the design never passed timing analysis?