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Altera_Forum's avatar
Altera_Forum
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13 years ago

Math calculations in VHDL

Hi all, I need a little help with my design, there are a few issues that I'm trying to resolve. My design flow is as following: A signal is sampled by a 16bit A2D, multiplied by 2 another 16bit...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

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Got it, thank you.

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pls publish the code which u hv got