Math calculations in VHDL

you can use them, but like I said you cannot pipeline them, which will lead to an extremely low fmax.

In Fixed point your results are limited by the number of bits you have. So you cannot store irrational numbers and you will only get within 2^-f (where f is the number of fraction bits) of the actual result.

It sounds like you are more a software guy and not a hardware guy. Do you really need 32 bit integers? do you really need a 64 bit result? these numbers are getting very big and going to chew up a large chunk of your FPGA. have you analysed your algorithm to see if you really need all of the bits? can you cut down on accuracy anywhere?