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Altera_Forum
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13 years ago

Math calculations in VHDL

Hi all, I need a little help with my design, there are a few issues that I'm trying to resolve. My design flow is as following: A signal is sampled by a 16bit A2D, multiplied by 2 another 16bit...
Altera_Forum's avatar
Altera_Forum
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13 years ago

Hi Tricky, thank you for your reply.

The reason I said that there are fractions is because when I divide the 2 32bit integers I will probably get a fraction.

You mean that I should convert the 32bit integers to ufixed and then divide them and store the answer in a 64bit ufixed signal? I tried to do that but I got a strange error regarding the "/" operator, that's why I used the lpm_divide megafunction instead, which works for std_logic_vector.

If I'm not using the std_logic_unsigned package I get an error even for a "+" sign, where am I wrong? Have I included all the correct files from the fixed-point package?