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Altera_Forum
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14 years ago

Master Addressing Issues

Hey everybody,

I have a question concernig the Avalon-MM Master Interface in Qsys.

My Datawidth is 32 Bit and so I have a 4 Bit Byteenable Signal.

My Adresswidth is 32 Bit, too.

If I understood the Avalon Bus correctly, my Master should only do aligned addressing (0x00, 0x04, 0x08,...).

Here is my question now: Does this aligned adressing concern to Byte adresses oder (for my 32 Bit Master) double word adresses? Is it wrong if I send the DoubleWord Address 0x01 (meaning 0x04,0x05,0x06,0x07 in Byte Adressing) instead of sending the Byte Adress 0x04?

I hope you can understand what I mean..

Thanks so far.

Michl

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  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    The only other workaround I can think of is maybe if you switch the master over to using word addressing this problem might go away at any width of the master address. So you just statically shift the address right before presenting it to the fabric and changing that .tcl command to use words instead of symbols. The shift will be >> (log2(datawidth/8)).