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Altera_Forum
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14 years ago

Master Addressing Issues

Hey everybody, I have a question concernig the Avalon-MM Master Interface in Qsys. My Datawidth is 32 Bit and so I have a 4 Bit Byteenable Signal. My Adresswidth is 32 Bit, too. If I unders...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Yes I understand this, thanks. And my system is acting like you described in your last post.

But:

-With an adress width of 32 Bits Qsys handles the addresses as Double Word addresses

-With an adress width of 30 Bits Qsys handles the addresses as Byte addresses

And this without changing the behaviour of my master. So is there any switch int the .tcl-files where I can tell Qsys that my master is issueing byte adresses even with 32 Bit wide address signal? In fact thats exactly what it does NOT. :)

Its really strange but if I put an avalon master translator between my own master and all the other slaves of the system it recognizes the addresses as byte addresses. And yes, the two interfaces (master and slave) of the translator agent are set up equaly! So it seems to me that Qsys (or the fabric) does not recognize that my master is issueing byte access!!!