Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Mapping more out ports to one out port

I have a ram memory that consists of several memory units. Each memory unit has, among other ports, data_out port. Memory itself has data_out port and it passes data that comes from one of those memory units. If I try to map several data_out ports of memory units on data_out port of ram memory, an error comes out saying I can't assign more than one value to data_out port. So, how to solve that connecting problem?

Thanks.

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    --- Quote Start ---

    I have a ram memory that consists of several memory units. Each memory unit has, among other ports, data_out port. Memory itself has data_out port and it passes data that comes from one of those memory units. If I try to map several data_out ports of memory units on data_out port of ram memory, an error comes out saying I can't assign more than one value to data_out port. So, how to solve that connecting problem?

    Thanks.

    --- Quote End ---

    you need to use a switch to get data from relevant block or use rd en if available per block according to overall system read address.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    I made multiplexer and encoder. The output of encoder is the input of multiplexer, so it can decide which memory unit data to pass. But, I made those two as asynchronous entities... Is that wrong considering that memory should respond after exact number of clk periods? I don't quite understand when does signal gets it's next value...

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    Latency through the memory will depend on how you have set it up. Its not a big issue making an async mux if there are only a few inputs, but wider muxes should be clocked. However, at high clock rates, everything should be registered