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Altera_Forum's avatar
Altera_Forum
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12 years ago

Mapping more out ports to one out port

I have a ram memory that consists of several memory units. Each memory unit has, among other ports, data_out port. Memory itself has data_out port and it passes data that comes from one of those mem...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Latency through the memory will depend on how you have set it up. Its not a big issue making an async mux if there are only a few inputs, but wider muxes should be clocked. However, at high clock rates, everything should be registered