Altera_Forum
Honored Contributor
Honored Contributormaking first "adder" and "fir" - using lpm lib
hi, i have some problems with compiling using two different projects with eachother.
The first I've made was an adder. Therefor I've used the adder_sub_component in the quartus42/lib/lpm file and made my own body around it: code of adder --- Quote Start --- LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY lpm; USE lpm.all; ENTITY adder IS GENERIC ( width: integer := 10); PORT ( cin : IN STD_LOGIC ; clock : IN STD_LOGIC ; a,b : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0); outp : OUT STD_LOGIC_VECTOR (width DOWNTO 0) ); END adder; ARCHITECTURE arc OF adder IS SIGNAL cint : STD_LOGIC ; SIGNAL sumint : STD_LOGIC_VECTOR (width-1 DOWNTO 0); COMPONENT lpm_add_sub GENERIC ( lpm_direction : STRING; lpm_hint : STRING; lpm_pipeline : NATURAL; lpm_type : STRING; lpm_width : NATURAL ); PORT ( dataa : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0); datab : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0); cin : IN STD_LOGIC ; clock : IN STD_LOGIC ; cout : OUT STD_LOGIC ; result : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0) ); END COMPONENT; BEGIN outp <= cint&sumint(width-1 DOWNTO 0); lpm_add_sub_component : lpm_add_sub GENERIC MAP ( lpm_direction => "ADD", lpm_hint => "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=YES", lpm_pipeline => 1, lpm_type => "LPM_ADD_SUB", lpm_width => width ) PORT MAP ( dataa => a, datab => b, cin => cin, clock => clock, cout => cint, result => sumint ); END arc; --- Quote End --- next i wanted to make a fir-filter (the most simple thing ever) using my own adder. this is: the adder with first input is input signal of fir and second input is again the fir's input but with one clock time delay and the output of the adder is the output of the fir. code of fir --- Quote Start --- library ieee; use ieee.std_logic_1164.all; entity fir is GENERIC ( width: integer := 10); port( inp: in std_logic_vector(width-1 downto 0); clock: in std_logic; outp: out std_logic_vector(width downto 0) ); end fir architecture arc of fir is signal hulp: std_logic_vector(width-1 downto 0); component adder GENERIC ( width: integer); port ( cin : IN STD_LOGIC ; clock : IN STD_LOGIC ; a,b : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0); outp : OUT STD_LOGIC_VECTOR (width DOWNTO 0)); end component; begin fir1: adder generic map (width:= width); port map ( inp <= a, hulp <= b, outp <= outp, clock <= clock ); end arc; --- Quote End --- now this are my errors when compiling: comiling errors --- Quote Start --- Info: ******************************************************************* Info: Running Quartus II Analysis & Synthesis Info: Version 4.2 Build 156 11/29/2004 SJ Web Edition Info: Processing started: Tue Oct 30 15:02:42 2007 Info: Command: quartus_map --import_settings_files=on --export_settings_files=off fir -c fir --generate_functional_sim_netlist Error: Verilog HDL syntax error at fir.vhd(14) near text "architecture"; expecting ";" Error: Verilog HDL syntax error at fir.vhd(16) near text "component"; expecting "end", or "begin", or a declaration statement, Error: Verilog HDL syntax error at fir.vhd(27) near text ":="; expecting ")", or "," Error: VHDL error at fir.vhd(26): object "adder" is used but not declared Error: VHDL syntax error at fir.vhd(33): name used in construct must match previously specified name "fir" Error: Ignored construct fir at fir.vhd(4) because of previous errors Info: Found 0 design units, including 0 entities, in source file fir.vhd Error: Quartus II Analysis & Synthesis was unsuccessful. 6 errors, 0 warnings Error: Processing ended: Tue Oct 30 15:02:43 2007 Error: Elapsed time: 00:00:01 --- Quote End --- its realy strange that i get errors of VERILOG - and I'm programming in VHDL.. I know its a lot of text here but i hope someone can give me an answer! I'm using QUARTUS 2 webversion. thanks!
