Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

making first "adder" and "fir" - using lpm lib

hi, i have some problems with compiling using two different projects with eachother. The first I've made was an adder. Therefor I've used the adder_sub_component in the quartus42/lib/lpm file and...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

The first error:

--- Quote Start ---

Error: Verilog HDL syntax error at fir.vhd(14) near text "architecture"; expecting ";"

--- Quote End ---

Two lines up (line 12): 

end fir

Add a semicolon to that line.