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its realy strange that i get errors of VERILOG - and I'm programming in VHDL..
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That problem was fixed sometime between versions 4.2 and 7.2 (another reason to use the latest version). The 7.2 messages:
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Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
Info: Processing started: Tue Oct 30 15:56:51 2007
Info: Command: quartus_map --lower_priority --read_settings_files=on --write_settings_files=off verilog_warning_for_vhdl_design -c verilog_warning_for_vhdl_design
Info: Found 2 design units, including 1 entities, in source file adder.vhd
Info: Found design unit 1: adder-arc
Info: Found entity 1: adder
Error (10500): VHDL syntax error at fir.vhd(14) near text "architecture"; expecting ";"
Error (10500): VHDL syntax error at fir.vhd(16) near text "component"; expecting "end", or "begin", or a declaration statement
Error (10500): VHDL syntax error at fir.vhd(27) near text ":="; expecting ")", or ","
Error (10396): VHDL syntax error at fir.vhd(33): name used in construct must match previously specified name "fir"
Error (10523): Ignored construct fir at fir.vhd(4) due to previous errors
Info: Found 0 design units, including 0 entities, in source file fir.vhd
Error: Quartus II Analysis & Synthesis was unsuccessful. 5 errors, 0 warnings
Info: Allocated 155 megabytes of memory during processing
Error: Processing ended: Tue Oct 30 15:56:53 2007
Error: Elapsed time: 00:00:02
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Honored Contributor
