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Altera_Forum's avatar
Altera_Forum
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16 years ago

Macros with arguments in Verilog/SystemVerilog

Hi all, I want to used parameterized Verilog macros in my code. It looks somewhat as shown below: `define ACTIVE_EDGE posedge parameter ISO_SENSE=1; always @(`ACTIVE_EDGE iso...
Altera_Forum's avatar
Altera_Forum
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15 years ago

It appears you have too many "`" in the expression. In your first example, ACTIVE_EDGE expands to posedge, but in the second example ACTIVE_ISO_EDGE( sences[i]) expands to `posedge, so the result will be ``posedge.