M144K and M9K memory blocks combined

Thanks a lot kaz!!

library ieee;
use ieee.std_logic_1164.all;
library altera_mf;
use altera_mf.all;
entity tta_altera_onchip_ram_comp is
  generic (
    init_file_g  : string  := "init_data.mif";
    dev_family_g : string  := "Cyclone II";
    addrw_g      : integer := 10;
    dataw_g      : integer := 32
    );
  port (
      address : in  std_logic_vector (addrw_g-1 downto 0);
      byteena : in  std_logic_vector (dataw_g/8-1 downto 0);
      clken   : in  std_logic;
      clock   : in  std_logic;
      data    : in  std_logic_vector (dataw_g-1 downto 0);
      wren    : in  std_logic;
      q       : out std_logic_vector (dataw_g-1 downto 0)
      );
end tta_altera_onchip_ram_comp;
architecture SYN of tta_altera_onchip_ram_comp is
  signal sub_wireH, sub_wireL : std_logic_vector (dataw_g-1 downto 0);
  signal clk_enH, clk_enL, clk_enHD: std_logic;
  constant byte_size_c : integer := 8;
  constant bew_c       : integer := dataw_g/byte_size_c;
  constant widthad_a_in: integer := addrw_g-1;
  component altsyncram
    generic (
      byte_size              : natural;
      clock_enable_input_a   : string;
      clock_enable_output_a  : string;
      init_file              : string;
      intended_device_family : string;
      lpm_hint               : string;
      lpm_type               : string;
      numwords_a             : natural;
      operation_mode         : string;
      outdata_aclr_a         : string;
      outdata_reg_a          : string;
      power_up_uninitialized : string;
      widthad_a              : natural;
      width_a                : natural;
      ram_block_type		 : string;
      width_byteena_a        : natural
      );
    port (
      clocken0  : in  std_logic;
      wren_a    : in  std_logic;
      clock0    : in  std_logic;
      byteena_a : in  std_logic_vector (bew_c-1 downto 0);
      address_a : in  std_logic_vector (addrw_g-2 downto 0);
      q_a       : out std_logic_vector (dataw_g-1 downto 0);
      data_a    : in  std_logic_vector (dataw_g-1 downto 0)
      );
  end component;
begin
	
  q <= sub_wireH(dataw_g-1 downto 0) WHEN clk_enHD = '1' ELSE
	   sub_wireL(dataw_g-1 downto 0);
	   
  clk_enH <= clken and address(addrw_g-1);
  clk_enL <= clken and not address(addrw_g-1);
  altsyncram_component_high : altsyncram
    generic map (
      byte_size              => byte_size_c,
      clock_enable_input_a   => "NORMAL",
      clock_enable_output_a  => "BYPASS",
      intended_device_family => dev_family_g,
      init_file 			 => "UNUSED",
      lpm_hint               => "ENABLE_RUNTIME_MOD=NO",
      lpm_type               => "altsyncram",
      numwords_a             => 2**widthad_a_in,
      operation_mode         => "SINGLE_PORT",
      outdata_aclr_a         => "NONE",
      outdata_reg_a          => "UNREGISTERED",
      power_up_uninitialized => "FALSE",
      ram_block_type		 => "M9K",
      widthad_a              => widthad_a_in,
      width_a                => dataw_g,
      width_byteena_a        => bew_c
      )
    port map (
      clocken0  => clk_enH,
      wren_a    => wren,
      clock0    => clock,
      byteena_a => byteena,
      address_a => address(addrw_g-2 downto 0),
      data_a    => data,
      q_a       => sub_wireH
      );
      
   altysyncram_component_low: altsyncram
	generic map(
		byte_size	=> byte_size_c,
		clock_enable_input_a => "NORMAL",
		clock_enable_output_a => "BYPASS",
		init_file => init_file_g,
		intended_device_family =>dev_family_g,
		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
		lpm_type               => "altsyncram",
      numwords_a             => 2**widthad_a_in,
      operation_mode         => "SINGLE_PORT",
      outdata_aclr_a         => "NONE",
      outdata_reg_a          => "UNREGISTERED",
      power_up_uninitialized => "FALSE",
      ram_block_type		 => "M144K",
      widthad_a              => widthad_a_in,
      width_a                => dataw_g,
      width_byteena_a        => bew_c
      )
    port map (
      clocken0  => clk_enL,
      wren_a    => wren,
      clock0    => clock,
      byteena_a => byteena,
      address_a => address(addrw_g-2 downto 0),
      data_a    => data,
      q_a       => sub_wireL
      );
      
   delay:process(clock)
	begin
	if(clock'event and clock='1') then
		clk_enHD <= clk_enH;
	end if;
   end process;
      
end SYN;