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Altera_Forum
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13 years ago

M144K and M9K memory blocks combined

Hi, I am working on Stratix III EP3SL150F1152CN FPGA. I am trying to port a hardware with 524,287 bytes (4,194,296 bits) of data RAM and 2048 bytes (16,384 bits) of address ROM. The total capac...
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Altera_Forum
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13 years ago

Looks ok to me in principle since you are using clkenabe ANDed with MSB address while passing other address bits shared. Similarly switching data. You may need to check latency issues on data switch.