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Altera_Forum
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13 years ago

M144K and M9K memory blocks combined

Hi, I am working on Stratix III EP3SL150F1152CN FPGA. I am trying to port a hardware with 524,287 bytes (4,194,296 bits) of data RAM and 2048 bytes (16,384 bits) of address ROM. The total capac...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Obviously it looks like there are some device restrictions. You can manually split up your ram into 2 halves(one half using 144 block and one half using M9Ks. You will need a bit of logic to decode address and mux data on two halves.